Index: src/sdk/resources/lexers/lexer_verilog.sample
===================================================================
--- src/sdk/resources/lexers/lexer_verilog.sample (revision 0)
+++ src/sdk/resources/lexers/lexer_verilog.sample (revision 0)
@@ -0,0 +1,14 @@
+// D flip-flop
+module d_ff ( d, clk, q, q_bar);
+input d ,clk;
+output q, q_bar;
+wire d ,clk;
+reg q, q_bar;
+
+always @ (posedge clk)
+begin
+ q <= d;
+ q_bar <= ! d;
+end
+
+endmodule
Index: src/sdk/resources/lexers/lexer_vhdl.sample
===================================================================
--- src/sdk/resources/lexers/lexer_vhdl.sample (revision 0)
+++ src/sdk/resources/lexers/lexer_vhdl.sample (revision 0)
@@ -0,0 +1,42 @@
+--
+-- Sample preview code
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity shiftregister is
+ generic
+ (
+ left : boolean := false -- so shift right
+ )
+ port
+ (
+ clk : in std_logic;
+ rst : in std_logic;
+ en : in std_logic;
+ d : in std_logic
+ q : out std_logic_vector
+ );
+end shiftregister;
+
+architecture behavioral of shiftregister is
+ constant crcpoly : std_logic_vector(7 downto 0) := x"8D";
+
+ type utxstates is (idle, data, parity, stop);
+ signal utxstate : utxstates;
+begin
+
+ shift: process ( rst, clk ) begin
+ if rst = '1' then
+ q <= (others => '0');
+ elsif clk'event and clk = '1' then
+ if left then
+ q <= q(q'left - 1 downto q'right) & d;
+ else
+ q <= d & q(q'left downto q'right + 1);
+ end if;
+ end if;
+ end process;
+
+end behavioral;
Index: src/sdk/resources/lexers/lexer_vhdl.xml
===================================================================
--- src/sdk/resources/lexers/lexer_vhdl.xml (revision 0)
+++ src/sdk/resources/lexers/lexer_vhdl.xml (revision 0)
@@ -0,0 +1,126 @@
+<?xml version="1.0"?>
+<!DOCTYPE CodeBlocks_lexer_properties>
+<CodeBlocks_lexer_properties>
+ <Lexer name="VHDL"
+ index="64"
+ filemasks="*.vhd,*.vhdl">
+ <!-- #define wxSCI_VHDL_DEFAULT 0 -->
+ <Style name="Default"
+ index="0"
+ fg="0,0,0"
+ bg="255,255,255"
+ bold="0"
+ italics="0"
+ underlined="0"/>
+ <!--#define wxSCI_VHDL_COMMENT 1
+ #define wxSCI_VHDL_COMMENTLINEBANG 2-->
+ <Style name="Comment"
+ index="1,2"
+ fg="34,138,34"/>
+ <!--fg="160,160,160"-->
+ <!--#define wxSCI_VHDL_NUMBER 3-->
+ <Style name="Number"
+ index="3"
+ fg="160,882,45"/>
+ <!--fg="240,0,240"/-->
+ <!--#define wxSCI_VHDL_STRING 4
+ #define wxSCI_VHDL_STRINGEOL 7-->
+ <Style name="String"
+ index="4,7"
+ fg="0,0,255"/>
+ <!--#define wxSCI_VHDL_OPERATOR 5
+ #define wxSCI_VHDL_STDOPERATOR 9-->
+ <Style name="Operator"
+ index="5,9"
+ fg="0,0,128"
+ bold="1"/>
+
+ <!--#define wxSCI_VHDL_KEYWORD 8-->
+ <Style name="Keyword"
+ index="8"
+ fg="0,0,160"
+ bold="1"/>
+ <!--#define wxSCI_VHDL_USERWORD 14-->
+ <Style name="User keyword"
+ index="14"
+ fg="0,160,0"
+ bold="1"/>
+ <!--#define wxSCI_VHDL_ATTRIBUTE 10-->
+ <Style name="Attribute"
+ index="10"
+ fg="95,159,159"/>
+ <!--#define wxSCI_VHDL_STDPACKAGE 12-->
+ <Style name="Std Package"
+ index="12"
+ fg="255,0,255"/>
+ <!--#define wxSCI_VHDL_STDTYPE 13-->
+ <Style name="Std Type"
+ index="13"
+ fg="159,159,95"/>
+ <!--#define wxSCI_VHDL_IDENTIFIER 6-->
+ <Style name="Identifier"
+ index="6"
+ fg="0,0,0"/>
+ <!--#define wxSCI_VHDL_STDFUNCTION 11-->
+ <Style name="Std Function"
+ index="11"
+ fg="0,0,255"/>
+
+ <Style name="Selection"
+ index="-99"
+ bg="192,192,192"/>
+ <Style name="Active line"
+ index="-
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