Index: src/sdk/resources/lexers/lexer_verilog.sample
===================================================================
--- src/sdk/resources/lexers/lexer_verilog.sample	(revision 0)
+++ src/sdk/resources/lexers/lexer_verilog.sample	(revision 0)
@@ -0,0 +1,14 @@
+// D flip-flop
+module d_ff ( d, clk, q, q_bar);
+input d ,clk;
+output q, q_bar;
+wire d ,clk;
+reg q, q_bar;
+
+always @ (posedge clk)
+begin
+    q <= d;
+    q_bar <=  ! d;
+end
+
+endmodule
Index: src/sdk/resources/lexers/lexer_vhdl.sample
===================================================================
--- src/sdk/resources/lexers/lexer_vhdl.sample	(revision 0)
+++ src/sdk/resources/lexers/lexer_vhdl.sample	(revision 0)
@@ -0,0 +1,42 @@
+--
+-- Sample preview code
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity shiftregister is
+    generic
+    (
+        left          : boolean := false -- so shift right
+    )
+	port
+	(
+		clk           : in  std_logic;
+		rst           : in  std_logic;
+		en            : in  std_logic;
+		d             : in  std_logic
+		q             : out std_logic_vector
+    );
+end shiftregister;
+
+architecture behavioral of shiftregister is
+	constant crcpoly   : std_logic_vector(7 downto 0) := x"8D";
+
+	type   utxstates   is (idle, data, parity, stop);
+	signal utxstate    : utxstates;
+begin
+
+    shift: process ( rst, clk ) begin
+        if rst = '1' then
+            q <= (others => '0');
+        elsif clk'event and clk = '1' then
+            if left then
+                q <= q(q'left - 1 downto q'right) & d;
+            else
+                q <= d & q(q'left downto q'right + 1);
+            end if;
+        end if;
+    end process;
+
+end behavioral;
Index: src/sdk/resources/lexers/lexer_vhdl.xml
===================================================================
--- src/sdk/resources/lexers/lexer_vhdl.xml	(revision 0)
+++ src/sdk/resources/lexers/lexer_vhdl.xml	(revision 0)
@@ -0,0 +1,126 @@
+<?xml version="1.0"?>
+<!DOCTYPE CodeBlocks_lexer_properties>
+<CodeBlocks_lexer_properties>
+		<Lexer name="VHDL"
+				index="64"
+				filemasks="*.vhd,*.vhdl">
+                <!-- #define wxSCI_VHDL_DEFAULT 0 -->
+                <Style name="Default"
+						index="0"
+						fg="0,0,0"
+						bg="255,255,255"
+						bold="0"
+						italics="0"
+						underlined="0"/>
+                <!--#define wxSCI_VHDL_COMMENT 1
+                #define wxSCI_VHDL_COMMENTLINEBANG 2-->
+				<Style name="Comment"
+						index="1,2"
+						fg="34,138,34"/>
+						<!--fg="160,160,160"-->
+                <!--#define wxSCI_VHDL_NUMBER 3-->
+				<Style name="Number"
+						index="3"
+						fg="160,882,45"/>
+						<!--fg="240,0,240"/-->
+                <!--#define wxSCI_VHDL_STRING 4
+                #define wxSCI_VHDL_STRINGEOL 7-->
+                <Style name="String"
+						index="4,7"
+						fg="0,0,255"/>
+                <!--#define wxSCI_VHDL_OPERATOR 5
+                #define wxSCI_VHDL_STDOPERATOR 9-->
+                <Style name="Operator"
+						index="5,9"
+						fg="0,0,128"
+						bold="1"/>
+
+                <!--#define wxSCI_VHDL_KEYWORD 8-->
+				<Style name="Keyword"
+						index="8"
+						fg="0,0,160"
+						bold="1"/>
+                <!--#define wxSCI_VHDL_USERWORD 14-->
+				<Style name="User keyword"
+						index="14"
+						fg="0,160,0"
+						bold="1"/>
+                <!--#define wxSCI_VHDL_ATTRIBUTE 10-->
+                <Style name="Attribute"
+                        index="10"
+                        fg="95,159,159"/>
+                <!--#define wxSCI_VHDL_STDPACKAGE 12-->
+                <Style name="Std Package"
+                        index="12"
+                        fg="255,0,255"/>
+                <!--#define wxSCI_VHDL_STDTYPE 13-->
+                <Style name="Std Type"
+                        index="13"
+                        fg="159,159,95"/>
+                <!--#define wxSCI_VHDL_IDENTIFIER 6-->
+                <Style name="Identifier"
+                        index="6"
+                        fg="0,0,0"/>
+                <!--#define wxSCI_VHDL_STDFUNCTION 11-->
+                <Style name="Std Function"
+                        index="11"
+                        fg="0,0,255"/>
+
+				<Style name="Selection"
+						index="-99"
+						bg="192,192,192"/>
+				<Style name="Active line"
+						index="-98"
+						bg="255,255,160"/>
+				<Style name="Breakpoint line"
+						index="-2"
+						bg="255,160,160"/>
+				<Style name="Debugger active line"
+						index="-3"
+						bg="160,160,255"/>
+				<Style name="Compiler error line"
+						index="-4"
+						bg="255,128,0"/>
+				<Style name="Matching brace highlight"
+						index="34"
+						bg="128,255,255"
+						bold="1"/>
+				<Style name="No matching brace highlight"
+						index="35"
+						fg="255,255,255"
+						bg="255,0,0"
+						bold="1"/>
+				<Keywords>
+                        <!-- Primary keywords and identifiers -->
+                        <Set index="0"
+                            value="access after alias all architecture array assert attribute begin block body buffer bus case component
+                                configuration constant disconnect downto else elsif end entity exit file for function generate generic
+                                group guarded if impure in inertial inout is label library linkage literal loop map new next null of
+                                on open others out package port postponed procedure process pure range record register reject report
+                                return select severity shared signal subtype then to transport type unaffected units until use variable
+                                wait when while with"/>
+                        <Set index="1"
+                            value="abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor"/>
+                        <Set index="2"
+                            value="left right low high ascending image value pos val succ pred leftof rightof base range reverse_range
+                                length delayed stable quiet transaction event active last_event last_active last_value driving
+                                driving_value simple_name path_name instance_name"/>
+                        <Set index="3"
+                            value="now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector
+                                to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left
+                                rotate_right resize to_integer to_unsigned to_signed std_match to_01"/>
+                        <Set index="4"
+                            value="std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed
+                                std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives
+                                vital_timing"/>
+                        <Set index="5"
+                            value="boolean bit character severity_level integer real time delay_length natural positive string bit_vector
+                                file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic
+                                std_logic_vector X01 X01Z UX01 UX01Z unsigned signed"/>
+				</Keywords>
+				<SampleCode value="lexer_vhdl.sample"
+						breakpoint_line="32"
+						debug_line="35"
+						error_line="37"/>
+		</Lexer>
+</CodeBlocks_lexer_properties>
Index: src/sdk/resources/lexers/lexer_verilog.xml
===================================================================
--- src/sdk/resources/lexers/lexer_verilog.xml	(revision 0)
+++ src/sdk/resources/lexers/lexer_verilog.xml	(revision 0)
@@ -0,0 +1,116 @@
+<?xml version="1.0"?>
+<!DOCTYPE CodeBlocks_lexer_properties>
+<CodeBlocks_lexer_properties>
+		<Lexer name="Verilog"
+				index="56"
+				filemasks="*.v,*.verilog">
+                <!-- #define wxSCI_V_DEFAULT 0 -->
+                <Style name="Default"
+						index="0"
+						fg="0,0,0"
+						bg="255,255,255"
+						bold="0"
+						italics="0"
+						underlined="0"/>
+                <!--#define wxSCI_V_COMMENT 1
+                #define wxSCI_V_COMMENTLINE 2
+                #define wxSCI_V_COMMENTLINEBANG 3-->
+				<Style name="Comment"
+						index="1,2,3"
+						fg="34,138,34"/>
+                <!--#define wxSCI_V_NUMBER 4-->
+				<Style name="Number"
+						index="4"
+						fg="160,882,45"/>
+						<!--fg="240,0,240"/-->
+                <!--#define wxSCI_V_STRING 6
+                #define wxSCI_V_STRINGEOL 12-->
+                <Style name="String"
+						index="6,12"
+						fg="0,0,255"/>
+                <!--#define wxSCI_V_OPERATOR 10-->
+                <Style name="Operator"
+						index="10"
+						fg="0,0,128"
+						bold="1"/>
+                <!-- #define wxSCI_V_PREPROCESSOR 9 -->
+                <Style name="Preprocessor"
+                        index="9"
+                        fg="128,64,0"/>
+                 <!--#define wxSCI_V_IDENTIFIER 11-->
+                <Style name="Identifier"
+                        index="11"
+                        fg="0,0,0"/>
+                <!-- #define wxSCI_V_WORD 5 -->
+                <Style name="Instructions"
+                        index="5"
+                        fg="0,0,255"
+                        bold="1"/>
+                <!-- #define wxSCI_V_WORD2 7 -->
+                <Style name="Keywords"
+                        index="7"
+                        fg="128,0,255"/>
+                <!-- #define wxSCI_V_WORD3 8 -->
+                <Style name="Tagname"
+                        index="8"
+                        fg="0,0,0"/>
+                <!-- #define wxSCI_V_USER 19 -->
+                <Style name="User"
+                        index="19"
+                        fg="0,0,0"/>
+				<Style name="Selection"
+						index="-99"
+						bg="192,192,192"/>
+				<Style name="Active line"
+						index="-98"
+						bg="255,255,160"/>
+				<Style name="Breakpoint line"
+						index="-2"
+						bg="255,160,160"/>
+				<Style name="Debugger active line"
+						index="-3"
+						bg="160,160,255"/>
+				<Style name="Compiler error line"
+						index="-4"
+						bg="255,128,0"/>
+				<Style name="Matching brace highlight"
+						index="34"
+						bg="128,255,255"
+						bold="1"/>
+				<Style name="No matching brace highlight"
+						index="35"
+						fg="255,255,255"
+						bg="255,0,0"
+						bold="1"/>
+				<Keywords>
+                        <!-- Primary keywords and identifiers -->
+                        <Set index="0"
+                            value="always and assign begin xbuf buf bufif0 bufif1 case casex casez cmos
+                                default defparam else end endcase endfunction endmodule endprimitive endspecify
+                                endtable endtask event for force forever fork function if initial inout input
+                                integer join macromodule makefile module nand negedge nmos nor not notif0 notif1
+                                or output parameter pmos posedge primitive pulldown pullup rcmos real realtime reg
+                                repeat rnmos rpmos rtran rtranif0 rtranif1 signed specify specparam supply supply0 supply1 table
+                                task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg vectored wait
+                                wand while wire wor xnor xor"/>
+                        <!-- Secondary keywords and identifiers -->
+                        <Set index="1"
+                            value=""/>
+                        <!-- System Tasks -->
+                        <Set index="2"
+                            value="$readmemb $readmemh $sreadmemb $sreadmemh $display $write $strobe $monitor $fdisplay $fwrite $fstrobe
+                                $fmonitor $fopen $fclose $time $stime $realtime $scale $printtimescale $timeformat $stop $finish $save
+                                $incsave $restart $input $log $nolog $key $nokey $scope $showscopes $showscopes $showvars $showvars
+                                $countdrivers $list $monitoron $monitoroff $dumpon $dumpoff $dumpfile $dumplimit $dumpflush $dumpvars
+                                $dumpall $reset $reset $reset $reset $reset $random $getpattern $rtoi $itor $realtobits $bitstoreal
+                                $setup $hold $setuphold $period $width $skew $recovery"/>
+                        <!-- User defined tasks and identifiers -->
+                        <Set index="3"
+                            value=""/>
+				</Keywords>
+				<SampleCode value="lexer_verilog.sample"
+						breakpoint_line="8"
+						debug_line="10"
+						error_line="11"/>
+		</Lexer>
+</CodeBlocks_lexer_properties>
Index: src/src/main.cpp
===================================================================
--- src/src/main.cpp	(revision 4510)
+++ src/src/main.cpp	(working copy)
@@ -2895,14 +2895,14 @@
         case wxSCI_LEX_POWERBASIC: comment = _T(""); break;
         case wxSCI_LEX_FORTH: comment = _T(""); break;
         case wxSCI_LEX_ERLANG: comment = _T(""); break;
-        case wxSCI_LEX_OCTAVE: comment = _T(""); break;
+        case wxSCI_LEX_OCTAVE: comment = _T("#"); break; // or '%'
         case wxSCI_LEX_MSSQL: comment = _T(""); break;
-        case wxSCI_LEX_VERILOG: comment = _T(""); break;
+        case wxSCI_LEX_VERILOG: comment = _T("//"); break;
         case wxSCI_LEX_KIX: comment = _T(""); break;
         case wxSCI_LEX_SPECMAN: comment = _T(""); break;
         case wxSCI_LEX_APDL: comment = _T(""); break;
         case wxSCI_LEX_BASH: comment = _T("#"); break;
-        case wxSCI_LEX_VHDL: comment = _T(""); break;
+        case wxSCI_LEX_VHDL: comment = _T("--"); break;
         case wxSCI_LEX_CAML: comment = _T(""); break;
         case wxSCI_LEX_BLITZBASIC: comment = _T(""); break;
         case wxSCI_LEX_PUREBASIC: comment = _T(""); break;
